DFM

May 1, 2010

Using advanced planarity analysis to drive smarter filling strategies

Designers have been using dummy fill to address design for manufacturing for some time, but the process of simply wallpapering shapes into a design's "white space" to help it maintain planarity can no longer cope with the complex challenges presented at today's advanced process nodes. Not only is planarity harder to maintain, but there are [...]
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May 1, 2010

Using DFM for competitive advantage

The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
May 1, 2010

Manufacturing a profit

DFM is essential to differentiating your products in the market, says Luigi Capodieci
May 1, 2010

DFM matures

Engineering managers need to get their priorities in order for incoming process nodes, says analyst Gary Smith
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May 1, 2010

Not the one that got away

The purpose of this special issue of EDA Tech Forum is to try and cut through some of the confusion and even frustration that surrounds DFM as a concept. We cannot promise “DFM for Dummies,” but we do hope to give you a sense of how you might manage the process.
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April 14, 2010

Solving the next parasitic extraction challenge

A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]
April 14, 2010

Top-level MCMM closure for a multi-million-gate design

STMicroelectronics in Greater Noida, India recently completed an Omega2 set-top-box decoder IC targeted at HDTV markets. This article discusses how ST used Mentor Graphics’ Olympus-SoC software to address the closure challenges presented by a very large design. It describes how the design team used the tool suite’s chip assembly, concurrent multi-corner multi-mode (MCMM) analysis and [...]
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December 1, 2009

The A word

According to the International Monetary Fund’s (IMF) latest World Economic Outlook, the possibility of a ‘double-dip’ recession cannot yet be discounted even if current data show the world economy beginning to recover. The IMF’s main concern is that private demand (including consumer spending) is not showing enough strength to restore consistent global GDP growth by […]

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December 1, 2009
3D stacking with TSVs

Making SiP happen in 3D

System-in-package (SiP) used to be thought of as a ‘poor man’s system-on-chip’ (SoC). Not any more. The complexity involved in implementing various levels of functionality on a single SoC is reaching such levels that it is becoming increasingly difficult to justify the design and manufacturing costs. Similarly, the need to deliver products within equally tight […]

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September 1, 2009

System level DFM at 22nm

The article provides an overview of one common theme in the papers presented at a special session of the 2009 Design Automation Conference, Dawn of the 22nm Design Era. As such, we would recommend that readers wishing to access still more detail on this topic (in particular, on device structures for 22nm and project management […]

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