It may be necessary to move to three-dimensional 'FinFET' transistors for future process nodes, but what impact will this have on circuit design?
Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
Double patterning provides an alternative to using EUV lithography – making it possible to implement ICs on sub-28nm processes.
The launch of a broad-based IDM/foundry consortium that is to prepare for the shift to 450mm wafers already offers some hints as to the future shape of chip manufacturing and the planning demands it will impose on all design managers in the near future. The game is shifting from pay-for-capacity to outright pay-to-play for those [...]
Selective CVD growth of germanium-tin: a new approach for implementing stress in germanium-based MOSFETs
Belgian research institute Imec describes, for the first time, the selective chemical vapor deposition (CVD) of germanium-tin (GeSn) in a production-like environment using commercially available Ge and Sn precursors. The resulting GeSn layers with 8% Sn are defect free, fully strained and thermally stable for temperatures up to 500°C. The technique is used to implement [...]
By the time a serious lithography-related problem is identified at the fab, it is too late in the design process to make simple layout changes. To avoid or reduce design delays, Infineon Technologies uses lithography simulation to detect weak points in a layout and analyze the effect of lithography on the design’s electrical performance. Its [...]
Current shortages could switch in key markets by the end of the year.
DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then, the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents [...]
Fab owners are looking to bring down their energy consumption to match the greening of semiconductors themselves.
Nanotechnology's economic potential will only be harnessed through more basic research, according to a new report from the NSF. Paul Dempsey reports.
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