DAC 2012: ARM tips subthreshold power-gating technique

By Chris Edwards |  1 Comment  |  Posted: June 5, 2012
Topics/Categories: Conferences, Design to Silicon  |  Tags: , , ,  | Organizations:

ARM chief technology officer Mike Muller gave some hints on the direction the company is taking with very low-power designs as part of his keynote address at DAC in San Francisco with a tip on how to square the circle between the low-energy consumption of subthreshold circuitry with the need for higher performance.

The processor IP supplier is working closely with researchers at the University of Michigan on very low-power systems, demonstrated as devices such as the M3 wireless sensor mote.

“The architecture we are working on is a stack of multiple pieces of silicon. One technology is not the right answer for all the components in your system. Although we are heading for a world where people are talking about massive processing power and massive amounts of memory in these 3D structures, even simple systems will turn into multiple stacks,” said Muller.

The logic layers in these sensor motes are pushing the voltage below the 1V where we are today to try to get energy consumption down to the point where it is possible run them from a small solar cell. Subthreshold circuitry, which has been used in commercial designs by companies such as Toumaz Technology, takes the supply voltage down to the 300mV level or lower. In this region, active power consumption plummets.

“Subthreshold is OK if you want to build very low-power systems,” said Muller. But there is a catch: “It’s good if you have very, very low performance requirements. If you actually want to build higher performance systems, near-threshold is where you want to be. But if you are building to an aggressive power management strategy, you may not have enough power to run fast.”

But as the voltage moves up, so does the overall power consumption from both leakage and active switching. One way to counter this is to power down any cells that are not actively switching until they are needed again.

“If you power down gates you have to restore state when they need to be powered back up, and that takes time to read back in. There is a third way. You can put in two diodes that let the logic gates go subthreshold when the power is removed. It’s susceptible to noise but when you put power back on, it can be recalibrated to the right state.

“If you don’t have to recreate state on each clock cycle, can get to 250kHz with near-threshold logic for same power consumption as as subthreshold design that runs at a maximum of 10kHz.”

“It would be farcical to consider this for a 1GHz apps processor,” said Muller, but for very low-power systems the diode-isolation technique looks viable.

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