DAC2012: Sagantec offers lifebelt to 28nm users, path to 20nm libraries

By Luke Collins |  2 Comments  |  Posted: June 5, 2012
Topics/Categories: Conferences, Design to Silicon  |  Tags:

Sagantec is offering companies that have committed designs to non-yielding processes a way to migrate to other foundries.

According to Maarten Berkens, CTO, once designs have been targeted to a process, they are pretty much committed: “At 28nm, the design rules are fixed and the standard-cell libraries are fixed, so it will be a real problem to make a major change here.”

He added: “Two major Taiwanese foundries have libraries which are close to compatible so you can do a migration between the two.”

The Sagantec tools can also be used to migrate cell libraries between process nodes, and check finalised  layouts against evolving design rules to fix violations, but the process is getting more difficult.

“In the past you could jump from 90nm to 45nm in one step, but right now just to cross one generation gap is very difficult,” said Coby Zelnik, CEO.

Berkens added: “It is also a question of quality, so what is  important is how many incompatible process steps there are between nodes. There used to be one such step per transition but now for  the shift from 28nm to 20nm there are issues such as the impact of double patterning on metal and vias, and restrictions on poly for local interconnect, which make it very challenging.”

Zelnik added: “Everything you move, you hit a rule.”

Part of the problem of migrating 28nm libraries to 20nm processes is the complexity of the design rules, which are delivered as a 500 to 600 page book of layout constraints described in English and using what  could be up to a total of 10,000 variables. The foundries develop the rules and do some example cell layouts, but as Berkens says, it’s a trade-off between the rules needed to achieve yield, for example by restricting metal spacing to enable double-patterned lithography (Guide), and rules written to enable special cases, such as high performance.

“it’s an enormous effort,” said Zelnik. “You are fighting so many physical phenomena, trying to make something that was perceived to be impossible a few years ago work and there’s no way to make that easy.”

How good are migrated libraries when compared with those handcrafted for a particular process node? Berkens said: “We are still getting experience on the transition to 20nm but if you do a migration, about half of the cells are equal or better to hand-crafted and the other half are worse. If we get more experience i think we can do equal or better.

“One of the issues with making the transfer to 20nm is working out how to split critical features across two mask layers so that they can actually be patterned properly. Berkens says that Sagantec’s tool will automatically ‘color’ – that is, define how features ought to be split – for the critical metal layers, vias and poly.

Double patterning may increase performance variability due to potential misalignment between areas of a cell that have been patterned by two masks. Berkens says although this could be an issue in metal layers two and three, in practice these lines are often short and therefore the impact is limited.

Dense processes such as 20nm may have issues with interactions between adjacent cells, which can also be tackled by ‘coloring’ the design at the cell level to reveal which cells should be kept apart. This comes at a cost.

“Coloring at the standard cell level imposes a lot of restrictions,” said Berkens. “The standard cell has to be able to fit next to any other cell, so if you are using colouring you need to check all possible adjacencies, and the rules for doing that are getting complex – or just design with a larger margin.”

The challenges of actually partnering and yielding 20nm processes are also making foundries issue increasingly restrictive design rules.

Berkens argued that  concerns about restricted design rules are overplayed: “Restricted design rules have been around for as long as there has been EDA. Poly at 20nm is on a restricted layout which makes it easy to do  because it is just a grid, but this shifts the problem elsewhere, on to metal 1.”

Zelnik said that Intel probably has the most restricted design rules, because the fabs have the power to tell the processor designers what they can and cannot do with their layouts, in order to ensure manufacturability.  To a certain extent, tighter layout rules wouldn’t do the processor designers any good  because they would still find their layout options limited by power density issues.

Restricted design rules are a bigger problem for the foundries, who face demands from customers to allow more flexible layouts.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors