Archives

Yokogawa has pulled together power meter and oscilloscope functions into a hybrid instrument for teams working to increasingly stringent energy-usage regulations.

Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.

Inside Secure has developed a set of certification-ready hardware IP modules that can be used stand-alone or in conjunction with ARM's TrustZone

Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.

FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.

The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.

Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.

Highway1 has opened up Spring applications for its incubation service for hardware startups: trying to overcome the gap between prototype and product.

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.