June 8, 2015
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
June 8, 2015
Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
June 8, 2015
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
June 8, 2015
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
June 7, 2015
Spice regressions, library characterisation and yield analysis are all being promoted as suitable for running on the cloud
June 7, 2015
IBM to offer end-to-end IC design flow on its own infrastructure in PAYG EDA model.
June 7, 2015
Invionics will be using its software environment to create a custom tool within just two days at the 52nd DAC.
June 7, 2015
OneSpin Solutions has used its formal-verification technology as the basis for an app intended for ISO 26262 projects that analyzes the ability of a design to deal with fault conditions.
June 7, 2015
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.
June 7, 2015
CAST and SoC Solutions have teamed up to put together pre-integrated platforms, with designs that reach down into the 8bit space.
