Formal verification conference offers ARM, Broadcom, Imagination insights, online access
Conference addresses formal verification techniques at levels to suit beginners through to experts
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Altera uses hierarchical approach to speed up FPGA compiles
Altera is revamping the Quartus II software for its FPGAs with a mapping and synthesis engine aimed at the upcoming Gen 10 products, as well as adding a C/C++ front-end for system-level design.
VLSI Symposia delve into future process choices
Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
EEMBC starts work on IoT-node power benchmark
Benchmarking organization EEMBC has kicked off an effort to develop a set of performance tests for edge nodes for the Internet of Things (IoT).
Xilinx updates Vivado with CDC, faster verification, third-party flows, and lab edition
New version of Vivado adds verification features and speed, extends Zynq support
Safety compliance in hardware and software development focus of online/Munich conference
Online and physical conference focuses on achieving compliance with safety standards such as ISO26262, DO254, and DO178
Automotive integration led by cabling concerns, says NXP
Cabling and its weight are helping to drive integration and a shift towards wireless communication within cars, says NXP’s automotive CTO.
Cadence upgrades debug for system-level era
Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
Do you need more stress (analysis) in your life?
Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company’s U2U conference.
UltraSoC pushes debug over USB
UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.