Altera uses hierarchical approach to speed up FPGA compiles

By Chris Edwards |  No Comments  |  Posted: May 11, 2015
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

Altera is revamping the Quartus II software for its FPGAs with a mapping and synthesis engine that is intended to handle large projects better, as well as adding a C/C++ front-end for system-level design.

Albert Chang, manager of software and DSP product marketing at Altera, said the Spectra-Q engine has been designed for the upcoming Gen 10 FPGAs: “It’s focused on reducing the number of design iterations.”

Much of the focus of the Spectra-Q engine is on fixing the layout of blocks and subsystems while other parts of the design are reworked to ensure that the tools do not rework the placement on each full-chip recompile and disrupt timing. The engine uses a hierarchical approach similar to that used for tools intended for large SoCs. The same approach is used to support the ability to bring completed IP blocks, such as those in Altera’s communications interface library, into a design and treat them as finished components.

“I want to quickly drag and drop IP interfaces into my devices. By dragging and dropping them, while preserving the timing of these IPs, I can focus on my value-add,” Chang claimed.

Split placement

With Spectra-Q, Altera has decided to split the placement stage into two sections. One focuses on I/O structure; the second on detailed placement. The idea is to provide designers with a way to see if a proposed design will fit into a given FPGA and have the right mix of supply, ground, serial-channel and data pins as well as PLLs for each proposed clock domain.

“By having the periphery placer separate we can run it in real-time,” Chang said, improving the turnaround time versus the current situation, which performs this assessment as part of the compilation stage.

A tool called Blueprint acts as a front-end to the coarse placement and provides a form of floorplanning, allowing quick exploration of different I/O and clock configurations.

Although the engine provides the ability to lock cores once placed and routed, this will limit the flexibility to optimize timing and placement across hierarchical boundaries. So, blocks can be unfrozen and recompiled to provide the placement engine with more choices, at the cost of reverifying timing for the affected sections.

“For protocol and memory interfaces in particular, it makes sense to take advantage of the hierarchical database blocks and not have to worry about those [once placed],” said Alex Gribc, senior director of software and IP marketing at Altera.

Distributed compiles

To enable faster compiles the work can be distributed across multiple servers and the company claims the core engine is twice as fast as its predecessor. Chang said the subscription licence for Quartus II will make it possible to allocate the work to multiple machines, which could potentially be provided by commercial cloud-computing services, without taking out additional licences. “We are leveraging technology from the Design Space Explorer tool,” Chang said.

With the new engine, “a high-level design compiler is shared across all the different front-ends,” said Chang. These include the A++ front-end, which is aimed at C/C++ users, as well as the OpenCL tools designed for software programmers and the company’s DSPBuilder tool. The A++ front-end uses a similar approach to the CatapultC tool developed by Mentor Graphics and later acquired by Calypso Design Systems. With A++, designs are created using ANSI C/C++ with directives used to control implementation.

Altera is currently offering the Spectra-Q engine under an early access program but has released v15.0 of Quartus at the same time, bringing Hybrid Memory Cube and HDMI 2.0 IP support for the Arria 10 FPGAs and SoCs. The portfolio also includes an upgrade in features and device support for the JESD204B core, providing Arria V support to 9.255Gbit/s as well as Cyclone V support up to 5Gbit/s. IP debug toolkits for external memory interfaces (EMIF) and PCI Express are also available to help designers rapidly prototype and expedite qualifications with additional access points to perform test and debug on IP cores.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors