Real Intent tries to shift left on DFT
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.
DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
Live and on-demand videos as well as You Tube ‘tips and techniques’ clips form part of a wide ‘work at home’ support package from Mentor.
Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.
Leading electronic system design conference confirms move online this July with Covid-19 restrictions and concerns expected to persist.