Design kit for 10nm FD-SOI due out next year
Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
IP-XACT gets design-flow extensions
Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Old problems on a new scale
For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.
TSMC 16nm finFET, Ge 20nm p-finFET set for IEDM
TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December’s International Electron Devices Meeting.
Real Intent updates X verification tool
Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
Distributor builds ECAD-MCAD links with free software
RS Components is now offering a solid-modelling tool to work with its free PCB design tool to provide easier access to 3D mechanical design.
SNUG heads to Austin next week
Synopsys user meet in Austin carries forward themes from Boston event.
Intel tips 14nm processor, Quark core and SoC licensing plans
In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.
Speed boost for Palladium emulators
Cadence Design Systems has upgraded its Palladium emulators to a maximum capacity of 2.3 billion gates and 50 per cent higher performance.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.