Verification

May 1, 2009

A holistic approach to low-power verification

The article describes a dedicated low-power functional verification methodology, originally developed at STMicroelectronics (now ST-Ericsson). The article details the content, sequence and effectiveness of the methodology as it was tested on a 45nm system-on-chip design. In order of use, the main components are: A high-level verification language testbench Formal verification Rule checking C function library […]

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May 1, 2009

A pulsed UWB receiver SoC for insect motion control

The article describes the context and need for embedded operating systems that are more responsive to the power management demands placed on today’s electronic devices. It reviews the design objectives for the two main types of power management, reactive and proactive, and examines how both can be implemented. For decades, scientists and engineers have been […]

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May 1, 2009

Advanced RTL power-aware verification

Traditional verification tools struggle to deal with today’s increasingly sophisticated power management technologies. One major limitation is that they cannot deal with varying power states because they make a built-in assumption that devices are always fully powered on. Further, power-aware verification at the register-transfer level is proving increasingly problematic, although it is also becoming increasingly […]

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March 2, 2009

Multiple cross clock domain verification

Today‚Äôs system-on-chip designs often need to encompass multiple asynchronous clocks. This raises the problem of verification for the resultant clock domain crossings. It is becoming apparent that functional simulation alone is not up to the task. Instead, engineers need to consider hybrid methodologies, combining structural and functional verification approaches. The use of assertions is also […]

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December 1, 2008

Tightening the loop on coverage closure

The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so […]

September 1, 2008

Building reusable verification environments with OVM

This article reviews the reuse potential within the Open Verification Methodology, with special focus on four particularly fruitful areas: testbench architecture, testbench configuration control, sequences, and class factories.
September 1, 2008

Clock domain crossing: guidelines for design and verification success

Clock domain crossing (CDC) errors can cause serious design failures. These can be avoided by following a few critical guidelines and using well-established verification techniques. The guidelines include: When passing 1bit between clock domains: register the signal in the sending clock domain to remove combinational settling; and synchronize the signal into the receiving clock domain. […]

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June 1, 2008

Accentuate the practical

When engineers discuss the status and value of the Design Automation Conference (DAC), one topic tends to recur. Fairly or unfairly, the claim is that there has long been an inherent tension between DAC the technical conference and DAC the exhibition. In short, the technical conference has been seen as biased toward tool developers; the […]

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June 1, 2008

VHDL moves toward 4.0

Version 4.0 of the VHSIC Hardware Design Language was approved by Accellera and passed to the IEEE to begin its formal standards balloting process earlier this year. The article previews some of the key additions and extensions that form part of VHDL in the following areas: Property Specification Language Intellectual Property Protection Hierarchical names Extensions […]

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March 1, 2008

How VHDL designers can exploit SystemVerilog

SystemVerilog, the standard that originated from Accellera and is now IEEE1800, is not just for Verilog users. VHDL users can also improve their design processes using its proven verification features. Anyone involved in systemon- chip (SoC) design may face a mixed-language environment and will appreciate being able to leverage SystemVerilog with the VHDL portions of […]

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