Verification

The argument for an integrated approach to SoC verification

Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.

IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.