asynchronous design

May 19, 2014

On-chip clock strategies and GALS

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
March 20, 2012

Blindsided by a glitch

Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare a design’s RTL and gate-level netlists equivalent. This article describes Real Intent’s approach to capturing them.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors