![Chips on a wafer](https://www.techdesignforums.com/practice/files/2014/06/wafer-prototype-64x64.jpg)
Early tape-out: smart verification or expensive mistake?
Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?