Verification

Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.

The next boost to verification productivity will come from the integration of multiple strategies and tools.

Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification