PSL

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.

Introduction The emergence of the SystemVerilog and PSL assertion languages promises to improve the effectiveness of existing verification flows. First, assertions give better local observability of the functionality they represent. Second, the assertions augment the textual specification to provide a more formal, executable representation of the functionality. Third, since the assertion languages have common semantics […]