Prototypers get faster route to first clock tick
Prototyping is increasingly important as designers strive to prove the functionality of their complex ASICs, confirm their compliance with complex industry standards, and will work as intended when interfacing with the real world. The trouble is, it can take too long to set up a prototype and get it to ‘first clock tick’ – the point at which it starts being useful.
One issue faced by many FPGA prototyping systems is the degree to which they are aware of, and integrated with, the capabilities of the target prototyping hardware. Until that gap has been bridged, the prototyping process will remain subject to unnecessary delays and potential risks.
Our recently introduced ProtoCompiler tool was developed in response to customer concerns about these issues, and attacks them directly. The idea is to enable designers to get to the first tick of the prototype’s clock more quickly, and at lower risk, than before.
How does Synopsys’s ProtoCompiler achieve this? Well, first, the software has a deep understanding of the HAPS hardware, so it can optimize logic placement and partitioning. The latest HAPS systems can be big, too, supporting designs with more than 250 million ASIC gates. A proprietary pin multiplexing scheme boosts prototype performance, and using off-FPGA memory means that the combination of ProtoCompiler software and HAPS hardware can capture and analyze gigabytes of debug data.
ProtoCompiler has a deep technical knowledge of the HAPS hardware, including its configuration, clocking structures, and interconnect architecture. It also has its own pin multiplexing expertise built in. The software also uses a proprietary prototyping database to process RTL effectively, making it easier to use incremental and multi-processing techniques to speed design deployments and iterations.
Figure 1 A new data model enables multiple iteration points (Source: Synopsys)
What does this mean in practice? ProtoCompiler can undertake the area estimation, one step in the automated partitioning process, of a 36 million ASIC gate in less than four hours, compared with 22 hours in existing solutions. Thanks to the new data model and incremental modes, subsequent compiles are even quicker.
How can ProtoCompiler support 250 million ASIC gate designs? This is because it is possible to chain up to six HAPS-70 S48s to deliver 288 million ASIC gates (or 24 Xilinx Virtex-7 2000T FPGAs) in one synchronous system.
What keeps such large systems in step? Up to three HAPS systems can be chained together using standard control and data-exchange cabling. When you want to connect four or more HAPS systems, a separate synchronization module keeps everything in step, handling clock skew, reset distribution and configuration automatically. ProtoCompiler understands these hardware capabilities and knows how to use them to greatest advantage.
New partitioning technology
ProtoCompiler overcomes the challenge of partitioning large ASIC designs across multiple FPGAs, using a partitioning engine that you set up as follows:
- Create the target system to which you will compile.
- Establish basic constraints, such as defining blocks of I/O.
- Define the design clocks.
- Propose an interconnect structure, or let the tool work it out.
If you let the tool pick the interconnect structure you may get higher performance, because ProtoCompiler will maximize the use of interconnect to reduce the amount of pin multiplexing. ProtoCompiler can also work with an existing interconnect structure.
ProtoCompiler partitioning is fast – the 36 million ASIC gate example discussed above was partitioned in four minutes. The tool also tells you a lot about what it is doing, so that you can review the results and adjust your guidance to optimize the partitioning. I’ve tried letting the tool work out the partitioning for itself and it seems to find a solution almost every time. I also challenged it, for example by limiting it to using 100 I/Os (on two HT3 connectors) between FPGAs. ProtoCompiler quickly told me that the design could never be partitioned with my interconnect architecture.
Pin multiplexing for higher performance
ProtoCompiler can automatically use the HAPS High-Speed Time-Domain Multiplexing (HSTDM) scheme to enable high-performance pin multiplexing between FPGAs. The signals are packaged up, sent across the link and unpacked at the other side, within a system clock cycle. The performance of HSTDM is tested during the production of HAPS systems, and has to pass minimum standards. This means that HSTDM links will work in the same way, whichever version of HAPS you compile your design on to.
Figure 2 Eye diagram of HAPS SSTL Standard at 1.2Gbit/s (Source: Synopsys)
If you’re building a complex ASIC, you’ll want to know what is going on within it, and that means capturing a lot of debug data. ProtoCompiler extends the HAPS Deep Trace Debug capability, which uses off-FPGA memory to store debug data. It also provides multi-FPGA debug capabilities with various levels of visibility, depending where you are in the debug cycle.
Figure 3 Different versions of HAPS focus on system speed or debug capability (Source: Synopsys)
For example, you may want very wide debug visibility with fast incremental turn-around early in the design cycle. Later on, you may need very deep debug windows. ProtoCompiler offers both, including the ability to capture seconds of debug data, even on complex designs
For designers, both ProtoCompiler and HAPS represent significant steps forward in prototyping technology. But it is the combination of the two, and the awareness within the software of the hardware’s capabilities, and the facilities within the hardware that enable the software’s functionality, which make it a quicker way for designers to get to that all-important first tick of their prototype’s clock.