Mentor to use UltraSoC acquisition to drive in-life learning
Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
UltraSoC
The price of reliability is constant vigilance
Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.
IP partnership aims to crack down on physical hacks
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
Debug connects with manufacturing test to cut product recall costs
UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
Support for RISC-V expands at summit
This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
UltraSoC adds security checks to bus monitoring IP
UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
UltraSoC scales up debug architecture
UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures.
UltraSoC combines tools for cross-SoC debug and analysis
Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
UltraSoC delivers trace for RISC-V
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
PLATINUM SPONSORS
View All Sponsors