UltraSoC


June 19, 2017

UltraSoc donates trace format to RISC-V group

UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
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December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
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November 24, 2016

Codasip adopts UltrasSoC debug for RISC-V cores

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
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September 20, 2016

UltraSoC to support RISC-V

UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
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December 1, 2015

Ultrasoc tweaks debug technology to act as SoC burglar alarm

Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
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November 11, 2015

UltraSoC adds CoreSight and Ceva debug support

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
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September 10, 2015

Debug monitors look for deadlock

UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
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June 9, 2015

Debug life cycle expands with on-chip infrastructure

By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
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April 22, 2015

UltraSoC pushes debug over USB

UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
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