December 1, 2017
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
June 19, 2017
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
December 7, 2016
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
November 24, 2016
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
September 20, 2016
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
December 1, 2015
Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
November 11, 2015
UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
September 10, 2015
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
June 9, 2015
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
April 22, 2015
UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.