DDR


December 8, 2017

IP choice drives SSD controller design

Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
Article  |  Topics: Case Study, Blog - IP  |  Tags: , , ,   |  Organizations: ,
May 17, 2014

Cadence ports IP and qualifies tools for 28nm FD-SOI

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
March 5, 2014

Visual timing tool focuses on high-speed PCB signals

Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
January 30, 2013

Mentor updates HyperLynx for faster boards, more rules checking

Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
February 27, 2012

Synopsys verification IP launch has bite

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors