Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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