Webinar discusses SoC security, area, and power trade-offs
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
Blog Topics
White paper discusses optimising the efficiency of DDR memory subsystems
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
Benchmark effort to look at IoT security performance
EEMBC has launched a benchmarking effort to test the performance of security and crypto-functions on embedded devices.
IEDM explores faces of 3D monolithic integration
What will 3D integration look like? IEDM 2016 explored some of the options ranging from IoT sensors to advanced logic.
IMEC stacks nanowire transistors together on CMOS
IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
Overcoming electromigration analysis limitations for larger on-die power grids
Award-winning paper describes new strategy offering both greater speed and accuracy.
HiSilicon licenses onchip debug engine for SOCs
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Security group publishes first guidelines
The UK's IoT Security Foundation has published the first set of documents intended to provide best-practice guidelines for developers of embedded systems.
Codasip adopts UltrasSoC debug for RISC-V cores
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
Siemens agrees deal to buy Mentor Graphics
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.