Cadence packages VIP for ten protocols
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
IP
Ceva adds hardware to speed up deep learning
Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
UltraSoC to support RISC-V
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
Debut for safety-critical ARMv8 core
ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.
GlobalFoundries ports MRAM to 22nm FD-SOI
GlobalFoundries has introduced an embedded-MRAM option for its 22nm FD-SOI process: the 22FDX platform.
Synopsys adds ultra-low power security processor IP
Ultra-low power security processor IP includes defences against side-channel attacks, data and instruction encryption, DSP options for sensor processing and more.
Design trade-offs in using DDR4 memory for enterprise applications
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
SystemC materials move to Apache 2.0 license
Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
Cadence adds floating point to Fusion
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
The IoT dream behind SoftBank’s ARM purchase
SoftBank cites IoT as its main reason for buying ARM, but could it change the relationship between customers and the processor designer?
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