Ceva DSP multiplies execution units for MIMO 5G
Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
IP
Software brings secure IDs to almost any device
Intrinsic-ID has developed software that allows its PUF technology to be used in most systems that contain static memory together with a framework for managing secure keys in the supply chain.
Wafer expansion hits the buffers
What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
VLSI Symposia issue calls for papers
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
Webinar discusses SoC security, area, and power trade-offs
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
White paper discusses optimising the efficiency of DDR memory subsystems
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
HiSilicon licenses onchip debug engine for SOCs
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Codasip adopts UltrasSoC debug for RISC-V cores
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
ARM brings security to Cortex-M family
ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.
Serdes deal to push copper server interconnect to 100Gbit/s
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.