VLSI Symposia issue calls for papers
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
IP
Webinar discusses SoC security, area, and power trade-offs
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
White paper discusses optimising the efficiency of DDR memory subsystems
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
HiSilicon licenses onchip debug engine for SOCs
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Codasip adopts UltrasSoC debug for RISC-V cores
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
ARM brings security to Cortex-M family
ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.
Serdes deal to push copper server interconnect to 100Gbit/s
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
Portable stimulus gears up to accelerate verification
Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
Achronix moves into embedded FPGA
Achronix has decided to offer the FPGA technology it has developed as a set of embeddable cores.
Ceva aims to displace ARM in IoT nodes with combo processor
Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
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