IP choice drives SSD controller design
Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
IP
European teams explore 3D integration tradeoffs
Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
Workshop sees the RISC-V ecosystem expand
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
X-Fab cuts flicker noise for 180nm process
X-Fab has added a process module to its wide voltage- and temperature-range 180nm mixed-signal process that supports a set of transistors with lower 1/f flicker noise.
Near-threshold clock control aims to improve processor efficiency
Minima Processor is working on the first processor cores that will be customized to use its timing-control technology to push supply voltages into the near-threshold zone.
Arm plans secure reference architecture for Cortex-M
Arm is putting together a security framework that the company is assembling to support, at least initially, IoT devices based on the Cortex v8M architecture.
Microsemi sets up RISC-V partner program
Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.
Arm TechCon 2017 preview: Synopsys
Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
Group to build CCIX accelerator test chip
ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
Codasip adds IoT core to RISC-V line
Codasip has added a processor core aimed at low-energy IoT nodes to its growing portfolio of customizable designs based on the RISC-V architecture.