A look at some of the key techniques needed to ensue good code coverage during the verification of low-power SoC designs.
A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.
The vision of portable stimulus is to find a way to write tests that can be portable ‘vertically’ from IP block to subsystem to system, and ‘horizontally’ from simulation to emulation to silicon. However, applying portable stimulus to real chip designs is not trivial.
It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
Why developing an IoT design environment demands an integrated, top-down design flow that combines AMS, digital, RF, photonics, and MEMS design and verification tools.
Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
Autonomous vehicle functional verification needs to prove the predictable behavior, safety and security of complex SoCs and their associated software, sensors and actuators, demanding greater use of hardware emulation.
An IDE is critical to top quality refactoring. Here are some tips and examples of how to achieve that.
Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
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