EDA Topics

June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
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June 4, 2020
UVM - Universal Verification Methodology

UVM coding guidelines offer clarity in a complex world

These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
June 2, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

VHDL users also deserve efficient design and verification

More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
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May 29, 2020
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

Covid-19 rings changes for virtual working

Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
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May 29, 2020
runtime monitoring featim

How to use runtime monitoring for automotive functional safety

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
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May 26, 2020
cloud computing efficiencies with calibre for physical verification

How cloud computing is now delivering efficiencies for IC design

A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
May 7, 2020
CMP simulation dummy fill featured image

Keep chip designs on the level with CMP simulation and dummy fill optimization

This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
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May 6, 2020
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and inventor of its core technology. He has more than 20 years of experience in functional verification automation and is a pioneer in bringing to market the first commercially available solution for Accellera’s Portable Stimulus Standard.

Security: Making the unknown, known

How to combine formal and dynamic verification within an app to uncover security vulnerabilities.
April 24, 2020
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How to gain a competitive edge with advanced DFT

Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
April 21, 2020
reset domain crossing featured image

How to achieve accurate reset domain crossing verification

The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.

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