A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
How to combine formal and dynamic verification within an app to uncover security vulnerabilities.
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
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