Physical verification of package assemblies no longer hinders package adoption

By John Ferguson and Armen Asatryan |  No Comments  |  Posted: December 15, 2021
Topics/Categories: EDA - Verification  |  Tags:  | Organizations:

Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.

With the ever-continuing demand for greater functionality, lower power, higher performance, and smaller form factors, the limits of Moore’s Law are continually pushed. While advanced processes such as 3nm and even eventually 2nm will bring significant benefits because they do not increase the total reticle size, they come at a great cost, especially for a large system-on-chip (SoC). As a result, there has been a rapid increase in activity in the development of multi-die heterogeneous packages.

There has been a great deal of innovation in the process of combining heterogeneous die into a single package over the past several years: new approaches for combining and stacking components, changes to the ecosystem with the foundries engaging into the traditional outsourced semiconductor assembly and test (OSAT) and packaging arena, the beginnings of a chiplet infrastructure and ecosystem, and most recently, significant advances in the design space.

One area that has not traditionally garnered much attention has been in the physical verification (PV) of these heterogeneous environments.

The problem with heterogeneous physical verification

Validating that multiple components from varying processes are properly aligned and connected to ensure that the total combined system behaves electrically according to the intended design specification is no small feat. Generating a full layout from multiple sources, each with potentially different magnifications and rotations, can be daunting. Further, different structures may have layer mapping conflicts that can trip up conventional PV approaches.

The most common solution to these problems has been a mostly manual process that is both time-consuming and prone to human error. Design rule checking (DRC) and layout vs. schematic (LVS) decks are provided for each interface (die-to-die, die-to-interposer, die-to-chiplet, die-to-package RDL, etc.). Engineers must create a new layout associated with each die in question, alongside the interfacing layer or layers from its corresponding interface component. This step alone can be challenging when magnifications are required or when layer-map conflicts exist. Additionally, this activity is only sufficient for DRC (typically verifying that pins from the two interface layers are properly aligned to enable adequate connections).

The traditional LVS verification approach must cross several hurdles. First, LVS is built on the premise of a pre-existing and validated source netlist, but such a construct is still rare in the multi-die arena. The LVS process typically extracts a post-layout netlist to compare to the source netlist – a step that relies on texting of net names. However, net names often change across interconnected dies. The extracted-post layout netlist must also be compared to the source by matching device components and their pin connections, but many components in the multi-die environment may be passive, with no device pins to verify.

Because LVS requires some sort of device or component pin, and because the net names on either side of the interface may not match, a ‘pseudo-device’ (usually in the form of a resistor or capacitor) is extracted between the interacting interface layers and shapes to allow the extraction of a netlist. Comparing these netlists then requires insertion of a similar pseudo device into the source netlist. And this raises a question: if the source netlist is changed, does it really represent the original source connections?

The final and perhaps biggest issue with this entire approach to package LVS is that it still only verifies each individual interface. How can a design team ensure that the entire system is truly properly connected in context?

Fortunately, a solution now exists that has been proven on multiple production designs.

Calibre 3DSTACK

The Calibre 3DSTACK solution was built using the known and trusted Calibre nmDRC and nmLVS solutions, with the intent to perform circuit and layout verification multi-die assemblies in a way that enables heterogeneous die processes to co-exist without significant impact to the deck. It does this without relying on manual layout merging, and without requiring tedious effort around pseudo-devices to differentiate die pins.

The Calibre 3DSTACK process uses a description of the assembly to form a full assembly layout that resolves possible layer map conflicts. This assembly description can be manually created or generated automatically using a tool like the Siemens Xpedition Substrate Integrator (XSI). Once created, the assembly description can be reused across the design and verification ecosystem. Typically, only the interfacing layers of each component are required, although all layers can be included. A source netlist can be created in Verilog, SPICE, or even traditional package-style netlist formats, such as those generated by XSI.

While this assembly generation step itself is traditionally quite fast, recent enhancements in the Calibre 3DSTACK engine provide even greater performance gains. Once the assembly is generated, engineers can view it in the Calibre DESIGNrev environment in either the traditional x-y view or the cross-sectional x-z or y-z views to visually validate stacking. The Calibre 3DSTACK process then performs interface alignment checking across the designs in the assembly. Typical checks validate interface alignment and connectivity extraction across all the interfaces, pinpointing misalignment and connectivity errors. A fast and easy check for power-ground shorts is also incorporated. If required, deck writers can easily create customized cross-component checks, such as marker alignment checking, using existing SVRF constructs. The Calibre DESIGNrev viewer can be used to identify and debug all errors in the full context. The ability to run the Calibre 3DSTACK checking process and view results in the Calibre DESIGNrev environment can significantly reduce the number of iterations needed, as well as the time required to debug and resolve errors, minimizing total time to completion.

The Calibre 3DSTACK functionality also enables the verification of individual passive components, such as silicon interposers, chiplets, or package redistribution layers (RDLs). By verifying the interconnection between same labels, or even known or expected label changes on a passive component, engineers can be confident there are no shorts or opens within the specific element. The automated addition of pin-labels based on XSI pin maps, die or component LEF abstracts, or even final die GDS or OASIS databases, ensures that the passive nets are properly connected in context. This approach to package verification allows designers to begin iterating even before all components are readily available for final placement.

Finally, much like traditional SoC LVS, Calibre 3DSTACK functionality can be used to drive parasitic extraction. While typical dies may already be extracted, scenarios with very close vertical stacking, such as direct-bonding of silicon components, or insertion of silicon-based structures into a package RDL, can result in cross-component coupling that must be accounted for. The Calibre 3DSTACK process can automate the isolation of such interfaces, as well as generate the appropriate layer stack-ups and material properties from each individual component, for accurate extraction. Design teams can then apply parasitic extraction software like the Calibre xACT tool across those structures to automatically generate the appropriate post-layout extracted netlist for insertion into the full system.

Final static timing can be performed through the creation of hierarchical Verilog, including all components and extracted interface coupling components. For dynamic analysis, the Calibre 3DSTACK process automatically combines the post-layout assembly netlist with insertion of extracted netlists for each sub-component as needed.

Moving forward on physical verification

Physical verification of package assemblies has long been a stumbling block in the path of wider package adoption and use. The Calibre 3DSTACK infrastructure, with its unique approach for assembly-level layout generation and netlist extraction, provides a fast and easy-to-use approach that enables designers to ensure that their multi-die system satisfies all manufacturing requirements and will create working circuitry that accurately reflects the design specification.

Calibre 3DSTACK functionality has been successfully applied to multiple styles of heterogeneous systems without limitation. When integrated into a design flow with the Xpedition platform, Calibre 3DSTACK functionality can greatly ease the package design and verification process. And, as the industry considers the interrelated electrical impacts of stress, thermal and power issues, the production-proven Calibre 3DSTACK process will continue to evolve and remain a key component in 3DIC design environments.

Further reading

To learn more about the advances now being made in PV, read this white paper: Taking 2.5D/3DIC physical verification to the next level

About the authors

John Ferguson is the product management director for Calibre DRC applications at Siemens Digital Industries Software. John has extensive experience in the area of physical design verification. He holds a B.Sc. degree in Physics from McGill University, an M.Sc. in Applied Physics from the University of Massachusetts, and a Ph.D. in Electrical Engineering from the Oregon Graduate Institute of Science and Technology. John may be reached at johnDOTfergusonATsiemensDOTcom

Armen Asatryan is an R&D technical lead for the Calibre platform at Siemens EDA, a part of Siemens Digital Industries Software. Prior to joining Siemens EDA, he held a variety of R&D management positions in EDA startups, with a focus on database management for yield analysis tools and flow integration with P&R environments. Armen holds a M.S. in applied mathematics with a focus in Computer Science, and a Ph.D. in engineering from the Institute for Informatics and Automation Problems of National Academy of Sciences of Armenia. He can be reached at armenDOTasatryanATsiemensDOTcom

 

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