EDA Topics

How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.

Part three of our series looks at the choices you face as you decide whether to build or buy a board.

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy

Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.

AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?