Preparing for low-power verification success: setting objectives and measuring outcomes
Functionally verifying complex SoCs is an enormous challenge, and the challenge grows when multiple power domains are throttled or powered up and down for power management needs.
Figure 1 How the verification challenge has grown over the past two decades (Source: Synopsys)
Why is functional verification so much more complex with low power? Verifying a low-power design requires completely verifying all its exponentially-increasing power states. In designs without power management, Verilog (IEEE 1364) specifies how event scheduling is described and interpreted, and simulation assumes that the device is always on. In low-power designs, the challenge is to accurately reflect the intent expressed in UPF (IEEE 1801) specifications of how the device behaves in all of the required power states, and how it retains its state while doing so. These issues are further complicated in IP-based designs, in which IP blocks may have internal power-management strategies that must be verified to work alone and in the system context.
If you have to accurately verify an advanced low-power SoC in all its operating states, at all its clock rates, and during all its transitions between those states and rates, you’re going to need several things:
- A power-aware verification plan
- Specific UPF-based power-aware verification methodologies
- Natively low-power and voltage-level aware simulation and static-verification environments
- UPF- and power-aware debug tools
- Advanced verification management tools that understand how low-power design strategies affect the verification process
Perhaps the most important of all of these is the verification plan.
Figure 2 Low-power verification must be seamlessly incorporated in all four phases of coverage-driven verification methodologies (Source: Synopsys)
Planning for low-power verification
There are two phases of planning for power-aware verification: setting objectives and measuring outcomes.
The objective of power-aware verification is to ensure that:
- The behaviour of the power-managed chip matches the design spec
- The power intent expressed through UPF sufficiently captures the intended design behaviour in all low-power states
- The low-power design implementation matches the specification, and that its architecture, structure and behaviour are valid
Looking at the time-to-market goals that companies face, and the number of features getting packed into today’s SoC designs, we see two clear verification challenges with low-power designs:
- Being able to catch design issues as early as possible is crucial to taping out with confidence. Making sure low-power intent is properly specified and maintained throughout the design flow is a key concern in the overall power-aware verification flow.
- Reducing the length of the verification cycle is increasingly important to meeting project and time-to-market timelines. Increasing low-power demands on designs expand the number of features to be verified in a power-aware context and can impact the overall project timelines.
As designs get bigger and have more stringent low-power requirements, power-aware verification tools and methodologies are key to solving the challenges highlighted.
SoC verification involves a sustained effort to ensure that a design has achieved enough coverage, that is, that its key functions have been explored rigorously enough to ensure the best chance of finding bugs – given the time and verification resources available.
A coverage-driven verification approach enables the structured, measurable and manageable verification of complex SoCs, and depends on the quality and completeness of the coverage metrics used in constrained-random verification methodologies. When designs include power-management strategies, verification engineers must add a new set of coverage objectives, as follows:
- Are all the design’s low-power states defined and mapped in the UPF definition of the power-management intent?
- Have all of the required power states from the UPF been exercised?
- Do we see illegal states/transitions?
- Have all the isolation or retention strategies been exercised?
Relevant coverage metrics, based on the analysis of the low-power design intent expressed in the UPF file, must be created as part of this coverage-driven verification methodology. The low-power coverage metrics must then be collected, reviewed and debugged alongside the other user-defined coverage metrics.
Synopsys’ functional verification solution, including VCS simulation and Verdi debug, include automatic coverage for low-power networks and objects at RTL, completely inferred from the UPF design intent. Except for the dark blue boxes below, these are identical to traditional VCS/Verdi coverage flows.
Figure 3 VCS low-power coverage flow (Source: Synopsys)
Advanced low-power design is critical to meeting the demand for high-performance devices with extremely low power dissipation in markets as varied as mobile computing and enterprise data centres. Today, UPF provides a standard way to specify power intent, and natively integrated power-aware verification will have to ensure that the design and implementation and inferred power intent matches the design specification in all aspects and modes.
An efficient power-aware verification flow should be a combination of natively integrated power-aware verification tools and flows, and provide closed-loop, coverage-driven verification methodologies that help you decide when you have done enough to verify that your low-power design will work as intended in all its power-managed states.
About the author
Amol Herlekar is a senior staff engineer in the verification group at Synopsys. He joined Synopsys in 2007 and is responsible for low power technology, which includes advanced static checking, power-aware simulation and debug. Amol has more than 14 years of experience in semiconductor design and EDA industries. Prior to joining Synopsys, he was with TranSwitch working on communication SoCs, and later at ArchPro Design & Automation, working on low-power products. Herlekar has a Bachelor’s degree in engineering from IIT Kharagpur.