How new RTL floorplanning techniques speed physical design
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
EDA Topics
Speeding AMS verification by easing simulation debug and analysis
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Hardware emulation answers Brooks’ Law
What can you add to a challenging project without pushing out deadlines and muddling communication?
Bus contention and floating busses: Catch them before simulation
Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
Easing the use of APIs for verification IP stimuli
How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
Using end-to-end prototyping to reduce the impact of rising software content in SoCs
A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
Reachable or reached, covered or coverable – is it just semantics?
How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
Finite state machines: How to debug and verify them early in the flow
Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
FPGA design for functional safety
Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
2016 – A continuation of change
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.