How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
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