Scaling automated software testing with Virtualizer Development Kits
How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.
EDA Topics
The challenge of verifying the evolving Ethernet standard
A look at the challenge of Ethernet verification as data rates rise and the standard is applied in a wider variety of applications.
Accelerating PCIe verification
A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.
How to maximize productivity with faster, high-capacity RTL synthesis
New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
Case study: Analyzing an electric vehicle powertrain using virtual FMEA
How the powertrain of an electric vehicle is modeled first in software, then elaborated using virtual hardware running target code, to enable virtual FMEA with rich data-gathering and analysis capabilities.
What’s cooking at the Flash Diner?
Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
FMEA in automotive software development using virtual prototyping, physical modeling and simulation
How fault mode and effect analysis (FMEA) can be performed on a virtual prototype of an automotive system containing mechanical, electrical, analog and digital models, including the microcontroller running the same software as will be used in the car.
Exploiting the power of reset in formal verification
The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
How to expose X-optimism issues in ASIC and FPGA design
Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
Floorplanning complex SoCs with multiple levels of physical hierarchy
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs