An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
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