IC Implementation

August 7, 2014
Hitendra Divecha is senior product marketing manager at Cadence Design Systems

Dealing with parasitic-extraction challenges in finFETs and advanced nodes

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
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July 25, 2014
Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
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July 9, 2014
Intel's trigate is among the structures to be modeled by the revised BSIM4

One BSIM to rule them all

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
June 27, 2014

How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe

How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
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June 10, 2014
High-speed I/O eye diagram - thumbnail

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
May 30, 2014

How the right DFY flow enhances performance and profit

'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
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April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
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April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
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February 11, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.

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