FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
The encryption chain for today's highly collaborative designs needs to be managed with care.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
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