January 26, 2015
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
January 20, 2015
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
October 31, 2014
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
October 18, 2014
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
October 6, 2014
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
September 18, 2014
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
September 2, 2014
How EDA tools are evolving to make it possible to design with finFET processes.
August 29, 2014
EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
August 27, 2014
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
August 7, 2014
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.