Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
A look at how collaboration between design, process and tool development is becoming increasingly important to get the best out of the most advanced nodes.
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
These days, when it comes to innovation: The car's the star - not the stooge.
New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
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