IC Implementation

November 4, 2021
UPMEM-PIM-DRAM-featured-image

How UPMEM ensured effective power delivery for its processor-in-memory design

PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
October 21, 2021
Sherif Hany Mousa is a Principal Technologist in the Calibre Design Solutions division of Siemens EDA, a part of Siemens Digital Industries Software. Sherif previously held positions as a technical marketing engineer, analog quality assurance engineer, and IC design consultant for physical verification and analog/mixed signal applications. He has authored multiple publications and holds multiple patents in the fields of analog layout porting, hotspot detection and correction, and machine learning-assisted verification flows. Sherif is a senior IEEE member who holds an M.Sc. in Electrical and Communication Engineering, and is currently engaged in Ph.D. research, focusing on circuit analysis.

Advanced symmetry verification is a thing of beauty

Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
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September 13, 2021
Swathi Rangarajan is a principal product engineer in the Calibre Design Solutions division of Siemens Digital Industries Software, supporting the Calibre RealTime platform. She focuses on in-design sign-off Calibre DRC checking in custom and digital design tools. Before joining Siemens, Swathi was an application engineer focusing on custom and digital design tool suites. Swathi received her BS in electronics and communication engineering from India, and her MS in engineering from San Jose State University

Hit your tapeout schedules with in-design signoff DRC

Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
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June 21, 2021
LEF abstract vs GDS

Out-of-sync data issues in parallel design flows need automated design integrity checks

Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
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May 31, 2021
Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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April 6, 2021

The path to full functional monitoring

Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
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June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
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