machine learning

February 8, 2024
Ron Press is Sr. Director of Technology Enablement for Tessent at Siemens EDA. As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee. a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching and on 3D DFT.

How AI improves DFT, test and yield

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
September 7, 2022

NVMe-oF – The future of cloud storage

NVMe over Fabrics (NVMe-oF) extends the memory standard for burgeoning data traffic and the demands of AI and machine learning.
June 25, 2021
Tina Durgia is a Product Manager for AMS verification at Siemens EDA and is responsible for the Solido Characterization Suite. Tina holds a Master’s degree in Electrical Engineering from Santa Clara University and has more than 13 years of experience in EDA across various digital design products including static timing analysis, place and route, logic synthesis and power analysis.

Use machine learning and visualization to accelerate Liberty file verification

Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
March 1, 2021
machine learning solido featured image

Machine learning overcomes library challenges at the latest process nodes

From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
February 20, 2020
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and inventor of its core technology. He has more than 20 years of experience in functional verification automation and is a pioneer in bringing to market the first commercially available solution for Accellera’s Portable Stimulus Standard.

Verifying AI engines

How can we refine our approach functional verification to deal with the increasing number of systems that leverage artificial intelligence.
September 13, 2019
John Blyler is a Consulting Editor of Tech Design Forum and the Editor-in-Chief of Interference Technology. He spent the first half of his career as a hardware-system systems engineer and program managerand the second half as a technology journalist, science writer and educator. John is an affiliate professor of systems engineering at Portland State University and lecturer for UC-Irvine’s online IoT program.

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
August 9, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
March 13, 2019
Liberty Variation Format - Featured Image

Validating on-chip variation: Is your library’s LVF data correct?

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
January 28, 2019

Emulation for AI: Part Two

The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.

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