design for test (DFT)

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies

Characterizing standard-cell defect mechanisms helps improve IC testing

This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]

Poster sessions are all too often given Cinderella status at major conferences, but they often contain novel and interesting responses to current technology challenges. This article reviews five poster papers that were released at the 2010 International Test Conference ranging in topic from improved device interfaces for gigahertz test to IP security to the diagnosing [...]

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]