Chinese dates set for Asia-Pacific editions of Mentor Forum
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Archives
Cadence adds floating point to Fusion
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
IEDM alters schedule to keep abreast of process updates
The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
The IoT dream behind SoftBank’s ARM purchase
SoftBank cites IoT as its main reason for buying ARM, but could it change the relationship between customers and the processor designer?
EEMBC looks into heterogeneous compute
EEMBC has turned its attention to heterogeneous computing with plans to create a new set of benchmarks.
Mentor’s PADS family extended for AMS, DDR and electrical DRC
Mentor Graphics has added four new units to its PADS PCB family addressing increasing complexity in mainstream design.
DTCO points to sub-10nm optimizations
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
What’s the shortest time in the universe?
“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic. So, some design teams are turning to IP that started out as open source to provide more scope for experimentation.
RC extraction from ‘virtual fab’ models may speed PDK availability
Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
DFT to expand its role for long-term yield
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.