Plasmonics may point way to faster interchip comms
Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Backside metal defends against IR drop and side-channel attacks
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
Virtual emulation delivers verification for the latest storage devices
Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
Arm expands cloud migration on Arm-based machines at AWS
Arm is pushing more work onto Arm servers in the AWS cloud as it encourages EDA vendors to port their tools to the architecture.
Macronix proposes 3D to breathe life back into NOR flash
At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.
Chipmaking’s new environment presented at IEDM
Imec’s senior vice president of CMOS outlined future directions for the technology over the coming decade.
Mentor rebrands as Siemens EDA
Mentor, a Siemens business, has rebranded as Siemens EDA, almost almost four years after the EDA company was acquired.
OSVVM updates go into Riviera-Pro
Aldec updates tools to add support for the latest release of the VHDL verification methodology.
Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)
Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.