Codasip adopts UltrasSoC debug for RISC-V cores
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
Author Archives: Chris Edwards
Multicore Association to update performance-estimation standard
The Multicore Association has started work on the second version of its SHIM performance-modeling standard for SoCs.
Multicore standard works on fast communications
Work by the Multicore Association to provide a standard way for applications running on different processors to communicate with each other is leading to active implementations.
Cadence maps out safety plan for semiconductor-design tools
Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
ARM brings security to Cortex-M family
ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.
Serdes deal to push copper server interconnect to 100Gbit/s
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
7nm finFET process techniques lead IEDM lineup
At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Portable stimulus gears up to accelerate verification
Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
ESD Alliance to describe system shift at DVCon Europe
Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
Achronix moves into embedded FPGA
Achronix has decided to offer the FPGA technology it has developed as a set of embeddable cores.