Take advantage of the automated refactoring of design and verification code
Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
Expert Insights
Achieving more efficient hierarchical DFT for Arm subsystems
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Spreading the word on formal in Bangalore
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Overcoming systemic design challenges for electric vehicles
EV design requires an ability to address interrelated tasks in areas such as architecture, performance, lifetime, range and charging speed.
Correct design and verification coding errors as you type
An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
A new formal proof kit for RISC-V processors
Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
The vocal persuader
In conversation with author and SEMICON West/ES Design West keynoter Bob Pearson on the challenges facing tech on external and internal communication.
A helping hand for design and verification
Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.
Speed up design and verification with a smaller layout
How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Why hyperlinks are essential for HDL debugging
Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
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