Blog Topics

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.

ARM is bringing the Trustzone security architecture to future Cortex-M processor cores, combining that with a version of AHB that will recognise the difference between secure and non-secure transactions.

Wind River aims to change its business model to collect money from cloud services for IoT instead of selling licences for embedded devices.

ARM has developed a version of its CoreLink on-chip interconnect IP intended to support systems based on its big.Little processors combinations that need a cache-coherent GPU connection with lower latency and higher peak throughput.

IP supplier CEVA has made a development platform intended to speed up the prototyping of IoT and similar devices based on its TeakLite-4 DSP core.

ARM has moved back into system-level modelling with the decision to buy the tools and models developed by Carbon Design Systems

Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.

...and why the semiconductor industry hasn't been singularitied down to one MegaSemis Inc even if that's what M&A data suggests.

IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.

Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.