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Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.

Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.

But the bridge standard's European backers still need greater support from the big EDA vendors.

High powered alliance develops TLM standards to address growing automotive and IoT concerns.

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.

ARM is bringing the Trustzone security architecture to future Cortex-M processor cores, combining that with a version of AHB that will recognise the difference between secure and non-secure transactions.

Wind River aims to change its business model to collect money from cloud services for IoT instead of selling licences for embedded devices.

ARM has developed a version of its CoreLink on-chip interconnect IP intended to support systems based on its big.Little processors combinations that need a cache-coherent GPU connection with lower latency and higher peak throughput.

IP supplier CEVA has made a development platform intended to speed up the prototyping of IoT and similar devices based on its TeakLite-4 DSP core.