IC Implementation

June 1, 2011

The challenge of analog, mixed-signal and custom physical implementation at 28nm

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]
Article  |  Tags: , ,
June 1, 2011

Opening up the dialogue

A bid for more interactivity is one of the program cornerstones for the 48th Design Automation Conference.
Article  |  Tags:
June 1, 2011

The new semiconductor ecosystem: wants and needs

Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.
Article  |  Tags: , ,   |  Organizations:
February 25, 2011

The fast run

DATE 2011 will be held this month around one of France's most active high-tech clusters. We preview some of the conference's highlights.
Article  |  Tags:   |  Organizations:
February 25, 2011

Demystifying analog and mixed-signal ASICs

The article reviews the design assessment process that a company should undertake when developing an analog-centric application-specific integrated circuit (ASIC). The authors argue that a number of myths surround strategies that incorporate a large amount of specialist analog design work, including evaluations related to cost and functionality. In particular, the need for differentiation in today's [...]
Article  |  Tags:
December 14, 2010

Characterizing PLL jitter from power supply fluctuations using mixed-signal simulations

Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL [...]
Article  |  Tags: ,
June 1, 2010

A matter of timing

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.
Article  |  Tags: , , ,   |  Organizations:
June 1, 2010

Fully grounded

Disneyland might be next door, but DAC 2010 is stressing a real-world perspective on chip design. We spoke to general chair Sachin Sapatnekar.
Article  |  Tags:
June 1, 2010

Usability made flesh

As usual, this issue includes our regular preview of the Design Automation Conference (DAC), taking place this year in Anaheim, California (June 13-18). However, given this journal’s particular focus on practical design information, I wanted to highlight one DAC strand up front. Indeed, given that the event has taken more than its share of criticism [...]
Article  |  Tags:
April 14, 2010

Winning at Whac-a-Mole: redesigning an RF transceiver

A team from RFMD describes a design upgrade for one of the company’s devices, the ML5800 transceiver. The chip is used in cordless telephones and has sold more than 20 million units. Because of constraints upon the different portions of the project and a wish to maximize reuse from the earlier chip, the company developed [...]
Article  |  Tags:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors