Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
Finding and fixing double patterning problems in 20nm designs
A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
Current techniques for modelling RF power amplifiers don't provide the dynamic range necessary to simulate their performance properly when used in the energy-saving envelope-tracking mode necessary to give LTE terminals a decent battery life.
It may be necessary to move to three-dimensional 'FinFET' transistors for future process nodes, but what impact will this have on circuit design?
Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
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