What is a finFET and why is it useful?
The finFET is a transistor design, first developed by Chenming Hu and colleagues at the University of California at Berkeley, which attempts to overcome the worst types of short-channel effect encountered by deep submicron transistors, such as drain-induced barrer lowering (DIBL). These effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel – in other words, to turn the transistor Off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around up to three of its sides, providing much greater electrostatic control over the carriers within it.
There are a number of subtly different forms of trigate transistor structure that are being described as finFETs. The architecture typically takes advantage of self-aligned process steps to produce extremely narrow features that are much smaller than the wavelength of light generally used to pattern devices on a silicon wafer. It is possible to create very thin fins – of 20nm in width or less – on the surface of a silicon wafer using selective-etching processes, although they typically cannot currently be made less than 20nm to 30nm because of the limits of lithographic resolution. The fin is used to form the raised channel. The gate is then deposited so that it wraps around the fin to form the trigate structure. As the channel is extremely thin the gate has much greater control over the carriers within it but, when the device is switched on, the shape limits the current through it to a low level. So, multiple fins are used in parallel to provide higher drive strengths.
Originally, the finFET was developed for use on silicon-on-insulator (SOI) wafers. Recent developments have made it possible to produce working finFETs on bulk silicon wafers and improve the performance of certain parameters. The steep doping profile used to control leakage into the bulk substrate has a beneficial impact on DIBL, although increased doping has a negative impact on variability.
Fully depleted SOI (Guide) transistors have been shown to offer comparable or better performance than finFETs. However, the relative compatibility of the bulk-silicon finFET with existing wafer fabrication processes and today’s wafer-supply chain favors the finFET for high-volume IC production at 22nm and below.
FinFETs have key advantages over planar bulk devices. They exhibit more drive current per unit area than planar devices, largely because the height of the fin can be used to create a channel with a larger effective volume but still take advantage of a wraparound gate.
The added performance capability of FinFETs can be used to achieve higher frequency numbers compared to bulk for a given power budget or lower power. The power reduction can come from two sources: reduced need for wide, high-drive standard cells; and the ability to operate with a lower supply voltage for a given amount of leakage.
What effect does the finFET have on design?
At such an early stage in its commercial development, the implications of the finFET are not entirely clear although results from Intel’s work suggest that the impact on digital design need not be that great if conservative approaches are taken. At the International Solid State Circuits Conference (ISSCC) in 2012, Intel described its approach as being one largely of design migration from circuits created for planar processes, using modelling and simulation to assess how the transition from planar to trigate would affect circuit performance.
A key difference between finFET-based design and that using conventional planar devices is that the freedom to choose the device’s drive strength is reduced, especially for devices that are close to the minimum size. Drive strength can only be improved during layout by adding more fins. The effective width of the device becomes quantized, and the quantization effect is worse for smaller transistors for which the next step up from the minimum-size device is one that is twice as wide. In addition, the minimum number of fins may be two in practical manufacturing processes. This is due to the self-aligned spacer processes that are used to create fins at tight pitches – each sacrificial spacer element that is deposited creates a pair of fins.
The Intel designers worked on the basis that whenever the optimum number of fins to achieve a particular drive strength was not an integer, they would round up to the next whole number – so that fractional fins were replaced with a full fin – rather than inserting transistors with less than optimal drive strength and risking the circuit not meeting timing.
A team from Infineon Technologies and Texas Instruments reported at the International Solid State Circuits Conference (ISSCC) in 2006 that the problem of fin quantization was potentially a bigger issue for SRAMs – as they would only use one fin to save space – than in analog circuits, where the use of minimum-sized transistors is far less crucial. The problem of using minimum-sized devices throughout an SRAM can create problems for static noise margin – reducing the ability of the system to reliably read a memory cell. Ideally, the pass gates would be weaker than the pullup and pulldown devices, particularly the latter.
One solution is to increase the fin count for pulldown devices but this increases area. Another is to weaken the pass gates by etching away the top surface of the gate – splitting the gate into a threshold-control and switching-control gate. This, however, increases process complexity. A third approach, as with sub-30nm planar CMOS processes is to use write-assist techniques – pushing the threshold voltage down temporarily by reducing the supply voltage.
Designers working on experimental finFET processes have reported other problems, such as self-heating – a problem noted again by Infineon researchers, this time at the International Electron Device Meeting (IEDM) in 2009. Recent work by IBM, albeit on SOI wafers, has indicated that self-heating is not likely to be a major issue.
FinFETs provide a number of advantages and several key disadvantages compared with bulk planar processes. Advantages include increased voltage headroom for circuits such as cascodes, lower gate resistance, which helps keep flicker noise under control, as well as improved matching, higher current drive and higher gain. However, the designer does not have the ability to control the channel as easily and the higher source/drain resistance cuts transconductance. On top of that, designers have little choice over voltages for I/O and have to develop more complex methods to achieve ESD immunity.
A further impact on design is the need to consider layout density in circuits that are usually quite sparse compared with digital layouts. Device density variation can lead to dishing – similar to the problems of copper metallization encountered in the move to 130nm processes. Similarly, the fins at the edges of a cluster suffer higher variability than those in the middle. These effects lead to greater need for the use of dummy-fill shapes to reduce the variation in density. Foundry processes tend to put dummy fins at the end of each transistor stack.
In terms of optimization for power, the finFET provides circuit designers with the opportunity to trade leakage for switching speed. Intel, for example, has deployed what it calls fast devices, with nominal leakage, medium-speed ‘quarter-leakage’ devices and slow ‘tenth-leakage’ devices. A problem facing process engineers is providing designers with a choice of threshold voltages to implement different circuits with different power-grade transistors at low cost.
At the International Electron Devices Meeting in December 2012, Intel presented details of a family of finFET designs that were optimized for high speed, low leakage and high (1.8V and 3.3V) operation in SoC designs.
As the finFET was conceived to be a device with almost no channel doping and back biasing the gate is very area inefficient even where possible, the main technique for adjusting threshold is to manipulate the work function of the gate. An alternative that will push up variability and may have a knock-on effect on fin pitch – and therefore cell density – is to dope the channel.
The lack of back or forward body bias control is one of the handicaps of today’s finFET structures versus FD-SOI. However, the larger ecosystem for finFET-based designs has made it more difficult for FD-SOI to compete.
Work is also underway at TSMC on introducing germanium into the fin of p-channel finFETs to improve the carrier mobility.
The finFET may have other, more subtle effects on design, at least at the cell-library level and for analog designers. Design rules will be further restricted to allow gates and fins to be placed on a regular grid. A key issue is compatibility between fin pitch and the pitch of the intra and intercell routing layers, leading to non-integer heights for standard cells if counted in terms of M2 tracks.
In their analysis of the finFET’s influence on layout, Rob Aitken and colleagues and ARM found: “Fin and metal pitches have different scaling pressures, so they have not tended to line up. For example, at 14nm GlobalFoundries has stated that it uses a fin pitch of 48nm and a metal pitch of 64nm. The same values are used in TSMC’s 16nm process.”
They added: “[Using GlobalFoundries’ numbers, only certain integral combinations of fin and M2 pitch are possible: six, nine, twelve, etc. A 6 track cell height is unlikely to be viable for two reasons. First, it will contain at most four active fins (2N and 2P), and second there is unlikely to be enough room to route internal signals for complex cells such as flip-flops. A library containing 6 active fins (3N and 3P) would be ten fins tall. This equates to 10×48=480nm, which is equivalent to 7.5 M2 tracks. This is likely to be the smallest feasible library in this type of technology, and comes with the obvious issues relating to non- integral track heights for physical design.”
In their analysis of routing techniques for sub-28nm processes, CMU and IBM researchers performed simulations to look at analog designs on finFETs that revealed issues with restricted design rules. “Our design simulations based on preliminary models reveal that FinFETs have a mixed impact on analog circuits. The restricted design rules expected to be seen in sub 20nm nodes greatly limit the allowable channel lengths for analog designers, which in turn can be worked around by stacking devices in series to emulate a long channel transistor, however, at the expense of increased parasitic capacitance.
“Conversely, FinFETs offer improved electrostatic control which translates to a higher intrinsic gain. Given these and several factors, some analog circuit topologies that have been considered obsolete may need to be revisited. For instance, topologies such as high gain linear amplifiers can be used in conjunction with switched capacitor circuits to balance performance for variation tolerance. Furthermore, emerging post-silicon tuning techniques such as self-healing and statistical element selection appear to be extremely valuable.”
Synopsys has a useful discussion on the practicalities of designing with finFETs, which is summarised here.
When can I use finFETs?
Unless you work for Intel or a research group with access to customized processes, there is no way to implement finFET-based designs commercially. This is expected to change with the move to 14nm processes, with the Common Platform foundry alliance (GlobalFoundries, IBM, Samsung) effectively committing to this shift in early 2012. GlobalFoundries has said it will introduce finFETs in its 14nm process – the devices will be optimized for mobile systems. The world’s largest foundry, TSMC, has yet to say when it will introduce finFETs although the technology is likely to be in place for the 14nm and may be brought forward to 20nm.
What are the risks of using finFETs?
Other than the difficulties of dealing with a new, 3D transistor design in terms of parasitic extraction and physical behavior, the major issue is cost: building a finFET uses a number of additional steps in a manufacturing flow that is already struggling to contain the cost of advanced lithography: double patterning (Guide) in the next few years, and possibly a move to EUV lithography in the second half of the decade. Figures presented by Qualcomm at IEDM 2013 indicated that the jump in cost to finFET was lower than that caused by the shift to double patterning from 28nm to 20nm. The back-end of line (BEOL) processes are more or less the same for 20, 16nm and 14nm technologies provided by the foundries.
Real-world finFETs do not have the same profile as research devices, at least not yet. Analysis by reverse-engineering specialist Chipworks found that the Ivy Bridge processors made by Intel use fins with a tapered profile. Device-level simulation by GSS, a spinout from research at the University of Glasgow, indicated that the shape of the fin yields a device with less favorable operating behavior than the ideal finFET profile, in which the fin walls are parallel to each other. The tapered fin tends to force most of the current into the very top of the fin at higher voltages, which could lead to reliability issues, and into the bulk of the fin in the off-state, which can lead to short-channel effects.
A further issue with bulk finFETs is higher variability than most research devices. Originally, the finFET architecture was conceived as being built on SOI wafers: the oxide layer provides a ‘stop’ for the etch processes used to define the raised channel fins. On a bulk-silicon process, control over fin depth is more difficult. The manufacturing issues appear to be manageable but leads to greater variability in transistor behavior versus SOI-based implementations.
Watch Chenming Hu explain finFETs and compare them with planar transistors built on ultrathin body SOI processes here.