Xilinx

February 27, 2015

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices

Article | Topics: IP - Assembly & Integration, Design Management | Tags: Altera, IP encryption, IP Integration, reuse, Vivado, Xilinx | Organizations: Synopsys

October 23, 2012

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.

Article | Topics: EDA Topics, EDA - ESL, IC Implementation | Tags: FPGA, ISE Design Suite, Matlab, place and route, programmable logic, Simulink, synthesis, SystemC, SystemVerilog, Verilog, VHDL, Virtex 7, Xilinx | Organizations: Xilinx