IC Implementation

October 21, 2013
Featured image for high level synthesis LP Part One

How high-level synthesis helps optimize low power designs – Part One

Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
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October 16, 2013
Piyush Sancheti, vice president of product marketing at Atrenta.

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
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October 11, 2013
Mentor Power Grid article featured image

Power grid analysis for 2.5D and 3D IC systems

PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
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October 8, 2013
Cadence EAD flow

End mixed-signal infinite loops with electrically aware design

Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
October 7, 2013
Adnan Hamid is co-founder and CEO of Breker Verification Systems. Prior to starting Breker in 2003, he worked at AMD as department manager of the System Logic Division. Hamid graduated from Princeton University with Bachelor of Science degrees in Electrical Engineering and Computer Science and holds an MBA from the McCombs School of Business at The University of Texas.

Think like designers to fill the SoC verification gap

Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
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October 2, 2013

Catching layout-dependent effects on-the-fly

New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
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September 24, 2013

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
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September 17, 2013

Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design

Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
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September 3, 2013

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
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August 12, 2013
Steve Smith of Synopsys

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
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