Sphere:  |  Tags: , , , , ,

What is VHDL?

VHDL is a hardware description language developed as part of a US Department of Defense initiative begun in 1980 to enable more rapid design of very high speed integrated circuits (the VHSIC Program), hence VHDL, for VHSIC hardware description language.

VHDL was intended to be more accessible than Verilog, which was initially a proprietary language. VHDL also includes constructs that makes it more suitable for system specification than the more IC-focused Verilog.

The first version of VHDL was ratified as IEEE standard 1076  in 1987, with the publication of a Language Reference Manual. The  language evolved  into IEEE1076-1993, which was more widely supported, and was updated again in 2000, 2002 and 2008.

VHDL got analog and mixed-signal extensions in 1999 with the ratification of IEEE 1076.1, an extension of the original IEEE1076-1993 specification. The AMS variant of VHDL was updated in 2008, thanks to a collaboration between the IEEE’s VHDL Analysis and Standardisation Group (VASG)  and Accellera, the EDA standards body. It was further extended in 2011, with the ratification of IEEE1076.1.1, which enables designers to use VHDL to model systems that use multiple types of energy – electrical, mechanical, fluidic etc.

What does it do and why?

VHDL is a rich language that can be used to describe the functions of a system or a chip.

This richness has been a drawback in some contexts: it is, for example, possible to define systems using parts of the language, such as floating-point data types or wait statements, that cannot be translated directly into hardware. For this reason, a common subset of VHDL (1076.6) was defined to constrain the language’s descriptive power to constructs that can be synthesised into hardware.

Oddly enough, the language also had to be extended before it could be used for ASIC design, because it didn’t support the multi-valued logic used in logic simulation. The introduction of IEEE 1164, based on a nine-value logic system defined by Synopsys, overcame this problem, and was eventually subsumed into  IEEE1076-2008.

On the other hand, the richness of VHDL can make it a powerful way to model and simulate complex systems.

Where can I use VHDL?

VHDL can be used to model systems and, by constraining the constructs you use to the synthesisable subset, as the starting point of  an ASIC or FPGA design flow.

Can I buy it?

The VHDL standards documents are available for sale through the IEEE website.

Who is involved with VHDL?

Accellera, which was founded with the merger of VHDL International and Open Verilog International in 2000, has worked on VHDL alongside the IEEE’s VASG, which is charged with maintaining and extending the IEEE 1076 standard.

What are the risks of using VHDL?

VHDL never gained the momentum necessary to take over from Verilog as the language of choice for ASIC design, although it has developed a following for FPGA design.

The risk now is that as languages such as SystemC and SystemVerilog mature, and their associated verification methodologies become more widely established, support for VHDL could dwindle.

Some vendors are standing against this tide: Aldec and Synthworks have teamed up  to develop a verification methodology for VHDL, called OS-VVM and explained here, that mirrors the Universal Verification Methodology developed for SystemVerilog.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors