IC Implementation

December 1, 2008

Combining yield and performance in behavioral models for analog ICs

The article describes an algorithm that combines performance and variation objectives in a behavioral model for a given analog circuit topology and process. The tradeoffs between performance and yield are analyzed using a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a signi?cant improvement in overall simulation time and ef? ciency compared to […]

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September 1, 2008

The state we’re in

UK-based analyst group Future Horizons has been organizing its international electronics forums for 17 years and they continue to provide an invaluable look into what the industry’s top tier of managers is thinking. It is one thing to get your own wise analysts to pronounce on tomorrow’s market, but it is something else entirely to […]

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September 1, 2008

Rapid prototyping for the 802.11 era

The 802.11 family of wireless local area network (WLAN) standards is becoming ubiquitous. Products for its various fl avors – up to and including its latest 802.11n incarnation – must reach the market as quickly as possible. This implies a need for rapid prototyping, typically on an FPGA platform. This article describes how the design […]

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June 1, 2008

Sensium: A 1V micropower SoC for vital-sign monitoring

This paper describes the main design components and methodology priorities for development of the Sensium system-on-chip for wireless body sensor networks. The device is targeted at vital-sign monitoring and related medical applications. The SoC integrates an ultra-low-power wireless ISM band transceiver, hardware MAC, microprocessor, I/O peripherals, memories, 10b delta-sigma, analog-to-digital converter and custom interfaces. The […]

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March 1, 2008

Efficient packet header parsing using an embedded configurable packet engine

Cswitch’s CS90 Configurable Switch Array device has an interconnect structure, the dataCrossconnect network, that delivers bandwidth at 40- 100Gbps for packet-based applications. For packet handling tasks, the chip includes embedded configurable blocks, Configurable Packet Engines, that support functions such as frame parsing, CRC and hashing, and fast address look-ups, all at up to 1GHz. For […]

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December 1, 2007

The simulation and design of software-defined radios

The paper discusses the simulation, design, and test of software-defined radios (SDRs), initially using a legacy 16QAM waveform, followed by a new SDR waveform -orthogonal frequency division multiple access (OFDMA). The SDR system’s error vector magnitude (EVM) is first analyzed and its performance is compared with the legacy waveform results. The implementation also includes the […]

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September 1, 2007

Designing for the real world

Lew Counts It is not unusual for analog circuit designers to exhibit a wistful air of ‘been there, done that’, even if you would never catch them wearing the t-shirt. That goes double for Lewis Counts, vice president of analog technology at Analog Devices and a fellow with the sector giant. “There are things they’re […]

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September 1, 2007

Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below

Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]

September 1, 2007

The hidden cost of EDA

There must be a better way to keep track of electronic engineering software licenses. EDA tools are very expensive, essential to R&D work, and must be properly maintained to ensure that commercial designs are completed on-schedule. Nevertheless, companies traditionally set aside little management time to put formal control systems in place for these assets. Consider […]

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June 1, 2007

Advances in fast-SPICE for mixed-signal SoC verification

Today, most SoC designs include both digital and analog components on the same chip, taking advantage of nanometer geometries. This demands that the current design flow bottleneck due to analog verifi-cation and integration is addressed in ways that enable this process to be completed both thoroughly and efficiently. SPICE simulation was accurate but slow and […]

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