August 5, 2015
System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
August 4, 2015
The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
March 24, 2014
An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.
August 12, 2013
3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
December 12, 2012
Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.
November 16, 2012
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
October 25, 2012
How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
October 23, 2012
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
July 5, 2012
Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.