IC Implementation

Disneyland might be next door, but DAC 2010 is stressing a real-world perspective on chip design. We spoke to general chair Sachin Sapatnekar.

As usual, this issue includes our regular preview of the Design Automation Conference (DAC), taking place this year in Anaheim, California (June 13-18). However, given this journal’s particular focus on practical design information, I wanted to highlight one DAC strand up front. Indeed, given that the event has taken more than its share of criticism [...]

A team from RFMD describes a design upgrade for one of the company’s devices, the ML5800 transceiver. The chip is used in cordless telephones and has sold more than 20 million units. Because of constraints upon the different portions of the project and a wish to maximize reuse from the earlier chip, the company developed [...]

Process design kit (PDK) standards are one area that could greatly help reduce the disproportionate time and effort required to realize the analog portion of a design. PDKs have existed for two decades and provide access to foundry-verified data files for such AMS design elements as parameterized layout cells (PCells). However, most have been constructed […]

The paper presents a fully parallel transistor-level full-chip circuit simulation tool with SPICE accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple nonlinear subdomains based on circuit nonlinearity and connectivity. A parallel iterative matrix solver is used to solve the linear domain while nonlinear […]

Our preview of the forthcoming Design Automation Conference concentrates on the User Track that makes its debut there next month. Given that it shares many of the objectives behind this journal, that is hardly surprising. However, it is not the only aspect of DAC that merits investigation. Also in the program, conference chair Dr. Andrew […]

The Design Automation Conference (DAC) returns to San Francisco’s Moscone Center, July 26th-31st, and it is hoped that its proximity to Silicon Valley will see attendances hold up well even in tough times. However, the organizers are looking to more than just geography to guarantee continued interest in chip design’s main annual gathering. This 46th […]

Circuit noise problems can originate from a variety of sources. By carefully examining attributes of the offending noise you can identify it’s source, thereby making noise reduction solutions become more apparent. There are three subcategories of noise problems: device, conducted and radiated noise. If an active or passive device is the major noise contributor, you […]

As the market continues to push for higher performance at lower cost, trusted personal devices (TPDs) must also be able to exchange greater volumes of data, voice or streaming video at ever higher bit rates, while transmitting and receiving securely under multiple telecommunication standards. Reductions in cost and time-to-market can only be achieved by integrating […]

The article describes an algorithm that combines performance and variation objectives in a behavioral model for a given analog circuit topology and process. The tradeoffs between performance and yield are analyzed using a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a signi?cant improvement in overall simulation time and ef? ciency compared to […]